CODEWITHSUNDEEP
system-verilog
venkat pasumarti
venkat pasumarti

Reputation: 128

using interfaces in systemverilog?

i have written a code in system verilog for interface. but it it giving me the error at clk. the error is Undefined variable clk.... code is error at always(posedge clk)

   interface simple_bus(input logic clk);  
     // Define the interface   
     logic req, gnt; 
     logic [7:0] addr, data; 
     logic [1:0] mode; 
     logic start, rdy; 
   endinterface: simple_bus 

   module memMod(simple_bus a); 
     // simple_bus interface port logic avail; 
     //logic clk; 
     always @(posedge clk) 
     a.gnt <= a.req & avail; 
   endmodule

when using clock in always block it is giving the error "Undefined variable: clk"

Upvotes: 1

Views: 819

Answers (1)

H.Modh
H.Modh

Reputation: 448

clk is input to the given interface simple_bus, you need to hierarchically access it. Such as a.clk.

So your module code would be:

   module memMod(simple_bus a); 
     always @(posedge a.clk) 
       a.gnt <= a.req & avail; 
   endmodule

Edit:
I have tried your code at my end and it's working. PFB exa code. 

interface simple_bus(input logic clk);  
     // Define the interface   
     logic req, gnt; 
     logic [7:0] addr, data; 
     logic [1:0] mode; 
     logic start, rdy; 
endinterface: simple_bus 

module memMod(simple_bus a); 
  // simple_bus interface port logic avail; 
  //logic clk; 
  always @(posedge a.clk) a.gnt <= a.req; 
endmodule

module main();
  logic clk;

  simple_bus sb(clk);
  memMod m(sb);

  initial repeat(10) clk = #5 ~clk;
endmodule

Upvotes: 1

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