Reputation: 664
What is the relationship between Makefile and Bash?
Example in Makefile you have:
CC = gcc
But if you type this in the shell, you get error:
~# CC = gcc
-bash: CC: command not found
Understandably, because there are spaces. But it works in Makefile.
Also, in Makefile you use command substitution $()
$(CC) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
which should be variable substitution $CC
or ${CC}
in bash.
So Makefile syntax and bash syntax are different, but they do seem related, for example $@
.
Upvotes: 0
Views: 1111
Reputation: 48874
There's no relationship - make
and bash
are two separate programs that parse distinct syntaxes. That they have similar or overlapping syntactic elements is likely due to having been developed around the same time and for some similar purposes, but they don't rely on the same parser or grammar.
Many distinct languages have shared language features either for ease of adoption or from imitation. Most languages use +
to mean addition, for example, but that doesn't make the languages related.
Upvotes: 5