CODEWITHSUNDEEP
verilogsynthesisdigital
clidre vandijk
clidre vandijk

Reputation: 57

synthesizable FF in Verilog with active low reset

I would like to synthesize a FF with a positive edge clock and active low reset. I wrote the following Verilog code:

module dff_rstL (q,qn,clk,d, clearL);
input  clk,d, clearL ;
output q,qn;
reg q;
always @(posedge clk or negedge clearL)            //asynchronous reset
 begin
    if (clearL) begin
        q <= d;             
    end
 else    begin       
     q <= 1'b0;                 
   end         
end
assign  qn=~q;
endmodule

But I get the following error during synthesis:

Cannot test variable 'clearL' because it was not in the event expression or with wrong polarity. (ELAB-300) * Presto compilation terminated with 1 errors. *

Do you know I can I make it synthesizable? Thanks a lot!!!

Upvotes: 0

Views: 3673

Answers (1)

Rahul Menon
Rahul Menon

Reputation: 792

the testing logic should be ~clearL and the first line/condition the reset block . 

module dff_rstL (q,qn,clk,d, clearL);
input  clk,d, clearL ;
output q,qn;
reg q;
always @(posedge clk or negedge clearL)            //asynchronous reset
 begin
    if (~clearL) begin
     q <= 1'b0;
    end
 else    begin
        q <= d;
   end
end
assign  qn=~q;
endmodule

Upvotes: 2

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