CODEWITHSUNDEEP
system-verilog
rasmus
rasmus

Reputation: 135

How do I use parameterized interfaces?

I am struggling to understand interfaces. At first, they seem simple enough, but once I started to work with parameterized interfaces, I just can't get the pieces to fall into place.

I have this interface:

interface my_if #( 
    parameter H_WIDTH = 64,
    parameter L_WIDTH = 8
);
logic [H_WIDTH -1:0]  a;
logic [L_WIDTH -1:0]  b;
logic                 ready;
modport in ( input a, input b, output valid);
modport out( output a, output b, input ready);
endinterface;

and I want to use that as a port in my module:

module my_module (
logic input clk,
logic input rst,
my_if.in    my_if
);

I don't see how to set the parameters of my interface.
I have tried the following instead of the above:

my_if(#.H_WIDTH((64), .L_WIDTH(64)) my_if()

and

my_if(#.H_WIDTH((64), .L_WIDTH(64)).in my_if()

which does not compile.

How do I then set the parameters of my interface?

The solution has to synthesize as this is not for verification.

Upvotes: 3

Views: 28328

Answers (4)

rasmus
rasmus

Reputation: 135

Actually this was the correct way in the first place:

module my_module (
logic input clk,
logic input rst,
my_if.in    my_if
);

this:

module my_module (
logic input clk,
logic input rst,
my_if # (.H_WIDTH(64), .L_WIDTH(64)) my_if()
);

is apparently not legal.

The parameters are set where the interface is connected to another module!

my_if # (.H_WIDTH(64), .L_WIDTH(64)) my_if_() is used like so:

module top (
input clk,
input rst
);

my_if # (.H_WIDTH(64), .L_WIDTH(64)) temp_if();

my_module inst_1
 (
clk           (clk),
rst           (rst),
my_if         (temp_if)
);


my_module inst_2
 (
clk           (clk),
rst           (rst),
my_if         (temp_if)
);

endmodule

Upvotes: 2

Alexander Rumyantsev
Alexander Rumyantsev

Reputation: 317

In the Synopsys DC flow it is recommended to create a simplified SystemVerilog wrapper to override interface and module paramters.

If you have access to Synopsys documentation see

HDL Compiler for SystemVerilog User Guide Bottom-Up Hierarchical Elaboration

Upvotes: 0

AndresM
AndresM

Reputation: 1373

You are almost there! In your top module (where you instantiate the interface), you only have to change:

my_if(#.H_WIDTH((64), .L_WIDTH(64)) my_if()

to

my_if # (.H_WIDTH(64), .L_WIDTH(64)) my_if()

And you should be good to go. The IEEE 1800-2012 LRM has a section (25.8 Parameterized interfaces) on this topic that you should go over.

Upvotes: 7

dave_59
dave_59

Reputation: 42623

You set parameters of an interface instance exactly the same way you set parameters of module; when it is instantiated. There is no syntax that allows you to set the parameters of an interface port. The parameter values are based on the interface instance connected to the port when instantiating the module.

This presents a problem when the top level module you are synthesizing has an interface port. It similar to when the top-level module has parameters that needs to be overridden. You need to check the synthesis manual of the tool you are using to see how to manually override the parameters.

Upvotes: 7

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