CODEWITHSUNDEEP
system-verilog
sara8d
sara8d

Reputation: 413

What are the advantages and the motivation of modports in a SystemVerilog interface?

I'm new to SystemVerilog.

I am reading the following tutorial:

https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/

I'm not sure what are the advantages and the motivation of modports in a SystemVerilog interface?

Upvotes: 4

Views: 2939

Answers (3)

rising_thunder
rising_thunder

Reputation: 11

Usually, interfaces don't need to capture direction information of signals used between modules or between a module and a testbench.

Example: Master/Slave

Master might need one set of signals as inputs and outputs and slave might need the same set of signals as outputs and inputs. So we use MOD PORTS inside the interface to group those signals and specify certain directions.

Mod-port example:

Interface with modports

interface arb_if (input bit clk);
  logic [1:0] grant, request;
  logic reset;

  modport TEST (output request, reset,
                     input grant,clk);

  modport DUT (input request, reset ,clk,
               output grant);
  modport MONITOR (input request, grant, reset, clk);

  endinterface

Upvotes: 1

Sanjeev Singh
Sanjeev Singh

Reputation: 151

Though simulators should check for direction during access, it is common for them to ignore it. Synthesis tools look at the direction for implementation.

Upvotes: 0

sharvil111
sharvil111

Reputation: 4381

Modports are used to specify the direction of signal with respect to a specific module/component.

They are also used to restrict access to certain signals from some modules/classes.

Usually testbench modport contains a bunch of stimulus-driving signals as output while the same signals are taken as input to the RTL. Also some response signals which are output to RTL are taken as input to modport.

Consider the example below:

interface my_interface(input logic clk, reset);

logic a;
logic b;
logic c;
logic sum;
logic carry;

modport tb  (input sum,carry,  output a,b,c,reset);
modport dut (output sum,carry, input a,b,c,reset);

endinterface

Here, testbench is allowed to drive a,b and c and reset. But it will be erroneous for testbench to drive sum and carry signals.

If we don't use a modport and accidentally the testbench/RTL drives their respective input signals, then it would result in unexpected behavior.

Henceforth modports are generally used to restrict the components for driving/sampling signals.

Also they allow the ease of different views of the signals within the interface. One can just look at modport and tell whether it is an input to a particular module/class or an output.

Refer this link about some more info.

Upvotes: 5

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