Reputation: 21961
gcc code.c -I/opt/local/include -L/opt/local/lib -lnetcdf -lm -fpic -o code
How can I convert this into a makefile? This is what I have right now:
IDIR =/opt/local/include
CC=gcc
CFLAGS=-I$(IDIR)
ODIR=obj
LDIR =/opt/local/lib
LIBS=-lm
code: $(OBJ)
gcc -o $@ $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~
Upvotes: 1
Views: 195
Reputation: 1009
I use more generic makefile:
NAME := $(shell basename $(shell pwd))
OBJ := $(NAME).o
CC := gcc
CFLAGS := -fpic
LIBS := m netcdf
LIB_DIRS := lib_dirs
SRC_DIRS := src
INCLUDE_DIRS := inc
LIB_FLAGS := $(patsubst %,-L%, $(LIB_DIRS))
LIB_FLAGS += $(patsubst %,-l%, $(LIBS))
INCLUDE_FLAGS := $(patsubst %,-I%, $(INCLUDE_DIRS))
SRC_FILES := $(shell find $(SRC_DIRS) -name *.c)
all:
$(CC) -c $(SRC_FILES) $(INCLUDE_FLAGS) $(LIB_FLAGS) $(CFLAGS) -o $(OBJ)
clean:
rm $(OBJ)
Notice:
Upvotes: 1
Reputation: 1721
Note that the following makefile would work
code: code.o
gcc code.o -o code
code.o: code.c
gcc -c code.c -I/opt/local/include -L/opt/local/lib -lnetcdf -lm -fpic
clean:
rm *.o code
Then it's just a matter of adding variables to the makefile. For example
OBJ=code.o
CC=gcc
IDIR=/opt/local/include
LDIR=/opt/local/lib
CFLAGS=-lnetcdf -lm -fpic
code: $(OBJ)
$(CC) $(OBJ) -o code
code.o: code.c
$(CC) -c code.c -I$(IDIR) -L$(LDIR) $(CFLAGS)
clean:
rm *.o code
Upvotes: 1