CODEWITHSUNDEEP
mipssystem-verilogsynthesis
Shankhadeep Mukerji
Shankhadeep Mukerji

Reputation: 668

How to synthesize hardware for SRA instruction

How should I design my SRA MIPS R3000 instruction, which shifts arithmetic the Reg[rt] by the shift amount. The shift amount is always a variable and not a constant, so I am just concerned how do I specify it in the code to make it synthesizable, when writing in Systemverilog. Since a variable cannot be synthesized, unless its value is known. Please correct me if my question is wrong.

Shift Word Right Arithmetic SRA: register rt are shifted right by shamt bits, sign-extending the high-order bits. The result is placed in register rd.

module ALU_SRA(
        input logic signed [31:0] rs,
        input logic signed [31:0] instr,
        input logic signed [31:0] rt,
        input logic signed [4:0] shamt,
        output logic signed [31:0] out);

        assign out = {`shamt{rt[31]}, rt >> shamt};

endmodule

Upvotes: 0

Views: 1505

Answers (2)

nguthrie
nguthrie

Reputation: 2685

Use an arithmetic right shift:

assign out = rt >>> shamt;

This is documented in section 11.4.10 Shift operators of the IEEE 1800-2012 Specification

Upvotes: 4

Kamil Rymarz
Kamil Rymarz

Reputation: 408

If you want to shift it in one cycle then you can do it like that: example

This will synthesize but you should check if it will match your timing requirements. If you need to extend shamt port then you need to write another shift function. Anyway if you don't need to shift in one cycle then you should add registers between each call to shift function for better timing.

Upvotes: 1

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