CODEWITHSUNDEEP
verilogsystem-verilogsynthesis
Shankhadeep Mukerji
Shankhadeep Mukerji

Reputation: 668

What will the assign statements get synthesized as?

I am interested to know what will these lines synthesize to? I am designing a direct mapped cache and using assign to separate my index, offset and tag bits. Will it synthesize to a demultiplexer? I did not mention the whole code since I just want to know how the assign statements will look after synthesis. In 8085 programming, I had read the term as 'address demultiplexing" so it was confusing.

module cache 
        (   input bit clk,
            input bit rst,
            input logic [15:0] address,
            input logic valid_in,
            input logic compare,
            input logic wr,
            input logic enable,
            input logic write_through,
            output logic dirty,
            output logic [4:0] tag_out,
            output logic [15:0] data_out,
            output logic valid_out,
            output hit
        );

            logic [7:0] index;
            logic [1:0] offset;
            logic [4:0] tag_in;

            assign offset = address[1:0];
            assign index  = address[9:2];
            assign tag_in = address[15:10];

    endmodule

Upvotes: 0

Views: 1721

Answers (2)

dave_59
dave_59

Reputation: 42623

Since there are no Boolean or arithmetic operators on the RHS of the assign, these statements just become conveniently named references for part selects of the address input. This is the same thing that happens when you instantiate a module and connect to its ports - signals can go through a name change. In fact, you could have you could have written your address input port declaration as

input .address({tag_in,index,offset}),

You still connect the address port when instantiating this module, but inside the module, it only has tag_in, index, and offset available to reference, not address.

SystemVerilog has the alias construct to make it more obvious that you are just creating a convenient names for a signal, instead of declaring another set of signals and using the assign statement. 

 alias offset = address[1:0];
 alias index  = address[9:2];
 alias tag_in = address[15:10];

Upvotes: 0

Vineeth VS
Vineeth VS

Reputation: 402

The above code will just simply get synthesized as wire's, since there are only assignments. I am not sure what de-multiplexing logic you are trying to create, but generally for a de-multiplexer you need to have a select signal based on which you decode which output should be enabled.

An example for a 1:2 de-multiplexer logic is given below

module demux_1_2(
   input [3:0] Q, 
   input Sel,
   output reg [3:0] D1, 
   output reg [3:0] D2
   );

always@(*) 
begin
   if(~Sel) begin 
      D1 = Q;
      D2 = 0; 
   end else begin 
      D1 = 0; 
      D2 = Q; 
   end
end

endmodule

Upvotes: 1

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