CODEWITHSUNDEEP
piceeprom
Sunkyue Kim
Sunkyue Kim

Reputation: 63

Erase/Write block size of EEPROM of PIC chips

First of all, sorry for bad English since my English skill is not that good...

Before the question, I want to explain my situation to help understanding.

I want to use EEPROM as a kind of counter.

The value of that counter would be increased very frequenty so I should consider endurance problem.

My idea is, write counter value on multiple address alternatively so cell wearing is reduced by N.

for example, if I use 5x area for counting,

Count 1 -> 1 0 0 0 0

Count 2 -> 1 2 0 0 0

Count 3 -> 1 2 3 0 0

Count 4 -> 1 2 3 4 0

Count 5 -> 1 2 3 4 5

Count 6 -> 6 2 3 4 5

...

So cell endurance can be extended by a factor of N.

However, AFAIK, for current NAND flash, data erase/write is done by a group of bytes, called block. So, if all the bytes are within single write/erase block, my method would not work.

So, my main question : Does erase/write operation of EEPROM of PIC is done by a group of bytes? or done by a single word or byte?

For example, if it is done by a group of 8-bytes, then I should make 8-byte offset between each counter value to make my method properly work.

Otherwise, if it is done by a byte or a word, I don't have to consider about spacing/offset.

Upvotes: 2

Views: 1273

Answers (1)

GJ.
GJ.

Reputation: 10937

From datasheet PIC24FJ256GB110 section 5.0:

The user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time.

However you can overwrite individual block several times if you left the rest of block erased (bits are one) and the privius content rest the same. Remember: you can clear single bit in block only ones.

How much will decerease the data retention after 8 writes in to single FLASH block I don't know!

Upvotes: 0

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