Multiple compilations with makefile

Question

I've been having serious trouble with Makefiles, I'm trying to run those commands in it and so far most of the changes I made resulted in "Nothing to be done for 'all'" no matter I change the lines, it just don't work. For example, PROG4 should have worked below but it says nothing to be done.

BIN_DIR = bin
LEX_DIR = lexyacc-code
LIB_DIR = lib
SRC_DIR = src
OBJ_DIR = obj

CC = gcc
BS = bison
FX = flex
CFLAGS = -I$(LIB_DIR)

SRCS = $(wildcard $(LEX_DIR)/calc3b.c)
SRCS2 = $(wildcard $(LEX_DIR)/calc3.y)
SRCS3 = $(wildcard $(LEX_DIR)/calc3.l)
SRCS4 = $(wildcard $(OBJ_DIR)/y.tab.c)
SRCS5 = $(wildcard $(OBJ_DIR)/lex.yy.c)

OBJS = $(patsubst $(LEX_DIR)/%.c,$(OBJ_DIR)/%.o,$(SRCS))


PROG = calc3b
PROG2 = y.tab
RM = rm -f

MVV="$(shell mv y.tab.c obj)"; echo $MVV


all: $(PROG2) $(PROG4) 


$(PROG): $(OBJS)
    $(CC) $^ -o $(PROG)

$(PROG2):
    $(BS) -y -d $(SRCS2)  

$(PROG4): $(CC) -c $(SRCS4) $(SRCS5) $(CFLAGS)


$(OBJ_DIR)/%.o: $(LEX_DIR)/%.c
    $(CC) $(CFLAGS) -c $< -o $@


clean:
    $(RM) $(PROG) $(OBJS)

Only PROG2 is working, basically for result I have header and source file which I tried to move specific folders but eventually I did it with 'mv' command (I know its against Makefile).

The commands are these:

bison -y -d calc3.y
flex calc3.l
gcc -c y.tab.c lex.yy.c
gcc y.tab.o lex.yy.o calc3b.c -o calc3b.exe

First command, I have one header and source as a result.

Second I have one source as a result.

Third I have 2 objects file as a result.

And fourth, I will have one executable.

Therefore, I also need to move those files to their specific folders.

Can anyone help me out with this? Thanks.

Answer 1

I think that the problem with $(PROG4) is that you forgot to put command on a new line with tab. In what you've showed above, the whole line of command is placed where it should be dependency but not command. Therefore, makefile executes no command for $(PROG4).