CODEWITHSUNDEEP
system-verilogctagsexuberant-ctags
justrajdeep
justrajdeep

Reputation: 923

How to generate ctags for system verilog?

I want to generate tags file for system verilog.

I found this really helpful link, and I was able to generate UVM tags file.

But my question is about SV. Since there is no separate sv files, the language is build into the compiler itself, how do i go about creating tags file for that?

Thanks in advance.

Upvotes: 4

Views: 12665

Answers (2)

Vitor
Vitor

Reputation: 1976

For improved support of SystemVerilog you can try Universal Ctags, where the Verilog parser was improved to also support SystemVerilog.

I also suggest that you use this Verilog/SystemVerilog Vim Plugin that also includes some basic omni-completion.

Disclaimer: most of this is my work. Your mileage may vary, but feel free to report issues and ask for improvements.

Upvotes: 2

dave_59
dave_59

Reputation: 42698

What was wrong with the link you provided? here are some others

https://verificationacademy.com/forums/systemverilog/ctags-systemverilog http://hackdut.blogspot.com/2015/03/ctags-and-vim-to-work-with-systemverilog.html

Upvotes: 3

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