Reputation: 24764
I try to compile many files and put the output in other directory. I have this Makefile
CC = gcc
BINDIR = bin
SRCDIR = src
SRCS = $(shell find $(SRCDIR) -name *.c)
BINS = $(patsubst $(SRCDIR)/%, $(BINDIR)/%, $(SRCS:.c=.exe))
all: $(BINS)
$(BINS): $(SRCS)
@mkdir -p $(BINDIR)
$(CC) -o $@ $<
clean:
rm -rf bin
and this directory structure
├── Makefile
└── src
├── bye.c
└── hello.c
when I use make, I get this
$ make
gcc -o bin/bye.exe src/bye.c
gcc -o bin/hello.exe src/bye.c
why the both times use src/bye.c
as source file?
and how I can compile any file?
Upvotes: 2
Views: 385
Reputation: 85767
Because your rule uses $<
. As explained in https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html:
$<
The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule (see Implicit Rules).
And src/bye.c
is the first element of $(SRCS)
.
Upvotes: 1