CODEWITHSUNDEEP
system-verilog
Tudor Timi
Tudor Timi

Reputation: 7573

Quote macro literal string argument inside string

I have the following macro:

`define check(CONDITION) \
  begin \
    if (!(CONDITION)) \
      $display("'%s' failed.", `"CONDITION`"); \
  end

And the following expansions:

module test;
  initial begin
    `check(0)
    `check(1 == 0)
  end
endmodule

They print the following:

'0' failed.
'1 == 0' failed.

If I have a condition over strings, though, then the macro expansion won't work properly. Concretely, adding the following line leads to a compile error:

`check("foo" == "bar")

What I would like, though, is to have the following printed:

'"foo" == "bar"' failed.

Is there a way to write the macro body that would allow this? I would like to avoid solutions where I have two macros, one where strings aren't allowed inside the condition and one explicitly for strings.

Upvotes: 0

Views: 1018

Answers (1)

dave_59
dave_59

Reputation: 42616

You can't do this with just one macro in SystemVerilog. It would take something like the qq() operator in PERL for this to work.

Upvotes: 1

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