Reputation: 8000
The Xeon page on Wikipedia says that Nehalem-based Xeon processors have an Integrated Memory Controller (IMC).
Volume 1: Basic Architecture listed on Intel® 64 and IA-32 Architectures Software Developer Manuals page also says in section 2.2.5: "Intel® Microarchitecture Code Name Nehalem":
— Integrated memory controller provides low-latency access to system memory and scalable memory bandwidth
So my understanding is that Xeon processors based on the Nehalem microarchitecture and newer microarchitectures all have an IMC. Is my understanding correct?
Upvotes: 2
Views: 376
Reputation: 44146
While the statement quoted refers to Nehalem Xeons only, there is no reason to believe that Intel took or is going to take a step back in the technology of their server processors.
In fact sampling same datasheets from the net for the successive families of Xeon processors gives:
Just by looking at the Table of Content it is easy to see that there is an iMC in each of those architecture. Skylake-Server replaces the ring bus with a mesh, with multiple memory controllers on-die connected to the mesh.
There are other Xeon families (E7, E3), I haven't checked them all but they should just be different scaling of the E5 in terms of frequency, TDP, cache and cores.
Upvotes: 4