Reputation: 3741
I have a blinking led design who use a differential clock input (xilinx AC701 kit). To instantiate the Xilinx differential buffer I'm using a BlackBox as explained by jkoening here:
class Top extends Module {
val io = IO(new Bundle{
val clock_p = Input(Clock())
val clock_n = Input(Clock())
val led = Output(Bool())
})
val ibufds = Module(new IBUFDS)
ibufds.io.I := io.clock_p
ibufds.io.IB:= io.clock_n
val blink = Module(new Blink)
blink.clock := ibufds.io.O
io.led := blink.io.led
}
That works, but On the Top verilog module I have a useless clock input :
module Top(
input clock,
input reset,
input io_clock_p,
input io_clock_n,
output io_led
);
...
Then on the target only io_clock_p
and io_clock_n
are used for clock input. clock
signal is useless. Is there a proper way to hide it ?
Upvotes: 1
Views: 758
Reputation: 3741
After discussion with Chisel3 team a feature has been added to support this.
The solution is to use a RawModule:
class Top extends RawModule {
val clock_p = IO(Input(Clock()))
val clock_n = IO(Input(Clock()))
val led = IO(Output(Bool()))
val ibufds = Module(new IBUFDS)
ibufds.io.I := clock_p
ibufds.io.IB:= clock_n
withClockAndReset(ibufds.io.O, false.B) {
val blink = Module(new Blink)
led := blink.io.led
}
}
A raw module has no implicit signal, and name are reflected «has it» in verilog generated file, no «io_» in prefix.
The source code of full blinking led project is available on this github project (blinking led project : blp).
Here is a french description of how to do it. To use this feature, last git master version of chisel3 must be used.
Upvotes: 2
Reputation: 6065
There is currently no way delete or even rename clock
and reset
on Chisel Modules. They are always there. Since Chisel uses positive-edge clocks, you could consider removing io_clock_p
and using clock
instead.
This is an oft-requested feature so it may be added in the future, but it is not currently supported.
Upvotes: 1