CODEWITHSUNDEEP
assemblyx86-64
Morty
Morty

Reputation: 1736

Is 64-bit direct memory operand possible on x86-64?

I was wondering if it is possible to encode an instruction like:

add rax,[address]

where <address> is a full 64-bit address pointing to a 64-bit value. NASM seems to simply truncate the address and encode it as a 32-bit address. The only form of 64-bit addressing (with a direct address) that seems to work is:

mov rax,[qword address]

which is encoded by NASM using REX.W=1 and special opcodes of MOV with direct addressing. Using REX.W with the add instruction merely makes it interpret the target address as containing a 64-bit value, but doesn't allow for the specification of a 64-bit address. But I am curious if there is another way.

(By the way, due to this problem I am for now using the RIP-relative addressing).

Can anyone confirm that the direct 64-bit addressing form is impossible?

Upvotes: 4

Views: 1476

Answers (2)

Albert van der Horst
Albert van der Horst

Reputation: 943

Remember that the 64 bits mode was a cludge of genius by AMD. In 1980 the Intel crew insisted that the INC REG16 (2 byte instruction) was too long, and wasted 16 of the 256 first page opcodes to make an alias with 1 byte. AMD repurposed this as a prefix with 4 bits available, wasting one byte on the rare occasion that a compiler cares to spare one byte.

The first bit indicates 1 for 64 bit operations. The other three bits left were used to specify wether 32 ot 64 bit registers were intended. Luckily the most complicated instruction with the sib, has a primary register, a pointer and a index, so three. These were used as switches, so geniality through simplicity.

In nearly all other respects the i386/pentium instruction set was not changed.

There is also a MOV instruction in code page one with implied register Ax. This also saves a byte compared with a two byte move 0x81 ..0x84, and is in modern insights superfluous, unlikely to be generated by compilers, and up for grabs. This instruction uses a 64 bit address, according to Cordes.

One of the myriad possibilities of the sib byte duplicates a simpler adressing modes. The shorter adressing mode now sports indirect addressing from the program counter.

So this answers your question, no deviation from 32 bits, no 64 bit addresses. The approved answer explains how 32 bit constants are interpreted where a 64 bit values is required.

Upvotes: -1

fuz
fuz

Reputation: 93004

The amd64 architecture has no addressing mode with a 64 bit displacement except in some special cases. Instead, use rip relative addressing which should be fine if your binary is less than 2 GB in size.

Upvotes: 4

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