CODEWITHSUNDEEP
linuxpagingmemory-mapping
X.Wang
X.Wang

Reputation: 39

Page Mapping Layout

I am confused about the 4-level page layout in X86-64 architectures. In the Linux source code implementation, they use: PGD(Page Global Directory) --> PUD(Page Upper Directory) --> PMD(Page Medium Directory) --> PTE

However, I also found another four-level page layout fro X86 architecture: PML4(L4) --> PDP(L3) --> PD(L2) --> PTE(L1)

So, is there anyone knows the difference between these two page layouts? May I consider the PML4 as the same component as PGD? If so the CR3 (PDBR) actually contains the address for PGD right?

A detailed answer will be greatly appreciated! Thanks in advance!

Upvotes: 1

Views: 543

Answers (1)

X.Wang
X.Wang

Reputation: 39

I am answering my own question here:

Multi-level page table structures are pretty common in the modern architectures. General term to describe the 4-level paging layout is: PGD-PUD-PMD-PTE, which is a widely used general terminology. Linux system source code actually also uses these terms to define the paging structures.

However, Intel uses its own terminology: PML4(L4) - PDP(L3) - PD(L2) - PTE(L1).

The ideas between these two are the same!

Upvotes: 2

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