VHDL implementing 2 seven segments at one

Question

Here is my assignment for class. Our task will be to design a VHDL component that provides basic stop watch functionality. Your design should start at zero and be able to count up to 20 on the right-most 7-segment displays (the other two displays should be blank except as noted below). Pressing the center button causes the count to start and stop. The down button resets the counter to 00. If the count reaches 20, the 16 leds on the board will create a complex victory pattern.

How would I display two numbers on different numbers on two different 7segs at the same time.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;


entity lab_3 is
Port ( 
-------------led output-------------------------------------
        led: out std_logic_vector(15 downto 0);
-------------button inputs----------------------------------
        btnc: in std_logic; 
        btnd: in std_logic; 
-----------7 seg outpus--------------------------------------------
        seg: out std_logic_vector(6 downto 0);      --MSB=a: LSB=g
-------------7 seg enables----------------------------------------
        an: out std_logic_vector(3 downto 0)

);

end lab_3;

architecture Behavioral of lab_3 is

------decimal seven segment display--------------------------CONSTANTS
    constant ZERO_7SEG: std_logic_vector(6 downto 0)  := "1000000";
    constant ONE_7SEG: std_logic_vector(6 downto 0)   := "1111001";
    constant TWO_7SEG: std_logic_vector(6 downto 0)   := "0100100";
    constant THREE_7SEG: std_logic_vector(6 downto 0) := "0110000";
    constant FOUR_7SEG: std_logic_vector(6 downto 0)  := "0011001";
    constant FIVE_7SEG: std_logic_vector(6 downto 0)  := "0010010";
    constant SIX_7SEG: std_logic_vector(6 downto 0)   := "0000010";
    constant SEVEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
    constant EIGHT_7SEG: std_logic_vector(6 downto 0) := "0000000";
    constant NINE_7SEG: std_logic_vector(6 downto 0)  := "0010000";
    constant TEN_7SEG: std_logic_vector(6 downto 0)  := "1000000";
    constant ELEVEN_7SEG: std_logic_vector(6 downto 0)  := "1111001";
    constant TWELVE_7SEG: std_logic_vector(6 downto 0)  := "0100100";
    constant THIRTEEN_7SEG: std_logic_vector(6 downto 0)  := "0110000";
    constant FOURTEEN_7SEG: std_logic_vector(6 downto 0)  := "0110001";
    constant FIFTEEN_7SEG: std_logic_vector(6 downto 0)  := "0010010";
    constant SIXTEEN_7SEG: std_logic_vector(6 downto 0)  := "0000010";
    constant SEVENTEEN_7SEG: std_logic_vector(6 downto 0)  := "1111000";
    constant EIGHTEEN_7SEG: std_logic_vector(6 downto 0)  := "0000000";
    constant NINETEEN_7SEG: std_logic_vector(6 downto 0)  := "0010000";
    constant TWENTY_7SEG: std_logic_vector(6 downto 0)  := "1111001";

-------------------led dance--------------------------------------                                                                                                                           `       constant step_one: std_logic_vector(15 downto 0):="0000000000000001";`
    constant step_two: std_logic_vector(15 downto 0):="0000000000000010"; 
    constant step_three: std_logic_vector(15 downto 0):="0000000000000100";
    constant step_four: std_logic_vector(15 downto 0):="0000000000001000";
    constant step_five: std_logic_vector(15 downto 0):="0000000000010000";
    constant step_six: std_logic_vector(15 downto 0)   :="0000000000100000";    
    constant step_seven: std_logic_vector(15 downto 0) :="0000000001000000";
    constant step_eight: std_logic_vector(15 downto 0) :="0000000010000000";
    constant step_nine: std_logic_vector(15 downto 0)  :="0000000100000000";
    constant step_ten: std_logic_vector(15 downto 0)   :="0000001000000000";
    constant step_eleven: std_logic_vector(15 downto 0):="0000010000000000";
    constant step_twelve: std_logic_vector(15 downto 0):="0000100000000000"; 
  constant step_thirteen: std_logic_vector(15 downto 0):="0001000000000000";
 constant step_fourteen: std_logic_vector(15 downto 0) :="0010000000000000";
  constant step_fifteen: std_logic_vector(15 downto 0) :="0100000000000000";
 constant step_sixteen: std_logic_vector(15 downto 0):="1000000000000000";      

---------------------active constants-----------------------------------
    constant active: std_logic :='1';
    constant inactive: std_logic :='0';
    constant ACTIVE_RESET: std_logic := '0';
    constant TERMINAL_VALUE: integer := 50000000;
-------------------internal connections-------------------------SIGNALS

    signal Clock:  std_logic;
    signal Count:  unsigned(7 downto 0);
    signal DividedClock: std_logic; 
    signal Digit0: std_logic_vector(6 downto 0);
    signal Digit1: std_logic_vector(6 downto 0);
    signal DigitSelect: std_logic; 
    signal led_dance: std_logic_vector( 15 downto 0);

-----------------clock divider----------------------------
begin 

    process(Clock)
    variable counter: integer range 0 to TERMINAL_VALUE;
    begin
        if (btnD=ACTIVE_RESET) then
            counter := 0;
        elsif (rising_edge(Clock)) then
            counter := counter + 1;
            if (counter = TERMINAL_VALUE) then
                counter := 0;
                DividedClock <= not DividedClock;
            end if;
        end if;
    end process;

     --------------------------counter-----------------------------          
process(Clock)

            begin
                if (btnD=active) then
                    count <= "00000000";

                elsif (rising_edge(Clock)) then
                    count <= count + 1;

                end if;
            end process;

-------------------BCD to 7seg--------------------------------            

            with count select 
                       Digit0 <=   ZERO_7SEG  when "0000000",
                                   ONE_7SEG   when "0000001",
                                   TWO_7SEG   when "0000010",
                                   THREE_7SEG when "0000011",
                                   FOUR_7SEG  when "0000100",
                                   FIVE_7SEG  when "0000101",
                                   SIX_7SEG   when "0000110",
                                   SEVEN_7SEG when "0000111",
                                   EIGHT_7SEG when "0001000",
                                   NINE_7SEG  when "0001001",
                                   TEN_7SEG   when "0001010",
                                   ELEVEN_7SEG when "0001011",
                                   TWELVE_7SEG when "0001100",
                                   THIRTEEN_7SEG when "0001101",
                                   FOURTEEN_7SEG when "0001110",
                                   FIFTEEN_7SEG when "0001111",
                                   SIXTEEN_7SEG when "0010000",
                                   SEVENTEEN_7SEG when "0010001",
                                   EIGHTEEN_7SEG when "0010010",
                                   NINETEEN_7SEG when "0010011",
                                   TWENTY_7SEG when others; 

             with count select 
                        Digit1 <=  ZERO_7SEG  when "0000000",
                                   ZERO_7SEG  when "0000001",
                                   ZERO_7SEG  when "0000010",
                                   ZERO_7SEG  when "0000011",
                                   ZERO_7SEG  when "0000100",
                                   ZERO_7SEG  when "0000101",
                                   ZERO_7SEG  when "0000110",
                                   ZERO_7SEG  when "0000111",
                                   ZERO_7SEG  when "0001000",
                                   ZERO_7SEG  when "0001001",
                                   TWO_7SEG   when "0010100",
                                   ONE_7SEG   when others;      

end Behavioral;

Answer 1

I suppose you need to connect either the Digit0 or Digit1 signal to the seg output port.

From my experience with such displays I assume that all four digits will show the pattern encoded by seg. In order to display different patterns for each digit, the idea is to quickly turn the individual digits on and off using the an output, so that only one of them is on at any given moment, while switching seg between Digit0 and Digit1 at the same time.

If the switching is done quick enough, it will not be apparent to the eye.

Answer 2

There are several design examples including SSDs at vhdl.us.