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cachingassemblyarm
Thomas Matthews
Thomas Matthews

Reputation: 57718

ARM LDM and STM wrt data cache and databus

I'm looking at an efficient method to copy 42 32-bit consecutive memory locations.
Note: A snapshot array is copied to a log array.

I'm using the LDMIA and STMIA pair (10 registers per instruction): 

LDMIA  R0!, {R2-R12}    ; Read 10 array slots\n
STMIA  R1!, {R2-R12}    ; Write 10 array slots\n

My questions:

  1. How do these instructions affect the data cache?
  2. Is the data bus locked during the entire load/store or is it only locked per 32-bit load / store?
    In other words, for the LDM instruction, does the ARM lock the data bus and load all the data into registers, or is the data bus only locked for each 32-bit transfer?

The code is running on an ARM Cortex A8 (Texas Instruments am3358).

I didn't see any hardware details in this page ARM Architecture Reference Manual

Upvotes: 1

Views: 235

Answers (1)

Igor Skochinsky
Igor Skochinsky

Reputation: 25288

You should check out the Cortex-A series programming guide from ARM. I don't have it here right now to quote but AFAIR it spends quite a lot of time on the topic of efficient memory handling if not specifically on the low-level details like bus locking (you probably need to look at the AHB/AXI documentation for that, but I don't believe it's really necessary here).

Upvotes: 2

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