CODEWITHSUNDEEP
vhdl
Joe Bragg
Joe Bragg

Reputation: 57

Can a Port Share the Name of the Signal it's Being Mapped to in VHDL?

Exactly as the title describes. There are asterisks surrounding the port and signal I am referring to. Is it conflicting in any way for a port to be named the same as the signal it is being mapped to? Or is it just good coding practice to have different names?

fml_fulladd_vhdl
    PORT MAP(
        C_in => C_in, -- this line
        x => x(3),
        y => y(3),
        s => s(3),
        C_out => C_out); -- and this line

Thanks to anyone who can offer help.

Upvotes: 2

Views: 1936

Answers (1)

QuantumRipple
QuantumRipple

Reputation: 1159

Yes, this is normal practice.

What you can't have is a signal within your architecture that has the same name as one of the ports of your associated entity. The same named signal as one of the ports on a component in the same level of hierarchy is fine. In fact, you can hook a port on your entity directly to a port on an instantiated component (same or differently named ports), no intermediate signals needed (assuming same direction ports and following type rules).

Be aware that if you cascade several of those full adders to add a multi-bit number (looks like you might be adding 4 bit numbers in your case), only one output (the output of the final instance) should drive the one bit C_out signal or you'll have multiple drivers. You'd need an intermediate signal to connect C_out to C_in of each fulladd instance.

Upvotes: 3

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