CODEWITHSUNDEEP
warningsvhdlxilinxsynthesis
Houghtonbrad
Houghtonbrad

Reputation: 45

Xilinx VHDL latch warning troubleshooting

Xilinx is inferring a latch for a VHDL code i've written. I've looked up the possible causes for this and found that it's often due to incomplete if or case statements. I've gone through and made sure to include else and when others statements, but i'm still receiving the warning. I believe this is also affecting another project i'm working on so i'd like to understand why this is the case. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity state_machine is
    port(trig, en: in std_logic; cstate,nstate: out std_logic_vector(0 to 2)); 
end state_machine;

architecture Behavioral of state_machine is
signal cstate_s,nstate_s: std_logic_vector(0 to 2);

begin
cstate <= cstate_s;
nstate <= nstate_s;

process(en, cstate_s)
begin
    if en = '1' then
        nstate_s <= "111";
        if cstate_s = "111" then
            nstate_s <= "011";
        elsif cstate_s = "011" then
            nstate_s <= "100";
        elsif cstate_s = "100" then
            nstate_s <= "101";
        elsif cstate_s = "101" then
            nstate_s <= "110";
        elsif cstate_s = "110" then
            nstate_s <= "111";
        else
            null;
        end if;
    else
        null;
    end if;
end process;

process(trig, nstate_s)
begin
    if rising_edge(trig) then
        cstate_s <= nstate_s;
    else
        null;
    end if;
end process;

end Behavioral;

WARNING:Xst:737 - Found 3-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Upvotes: 1

Views: 583

Answers (1)

Matthew
Matthew

Reputation: 13967

For there to be no latches synthesised when a combinational process is synthesised, there must be no path between begin and end process; where all the outputs of the process are not assigned. This is called complete assignment. An output of the process is any signal assigned anywhere within it.

You have such paths. When any path with your null statements are executed, the output of your first process (nstate_s) is not assigned to. Therefore, you will get latches synthesised. There is no point in just having a null statement. If you genuinely don't care what value is assigned to your outputs in these paths, assign the outputs to '-', which means don't care in VHDL.

By the way (assuming trig is a clock), your second process is not combinational (it is sequential) and so you don't need to obey complete assignment; your else branch is unnecessary.

Upvotes: 4

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