VHDL Entity port does not match type of component port

Question

I'm working on a MIPS-like CPU in VHDL with Xilinx Vivado. I have a component for my BranchControl module, which goes like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BranchControl is
    Port ( PL : in STD_LOGIC;
           BC : in STD_LOGIC_VECTOR(3 downto 0);
           PC : in STD_LOGIC_VECTOR (31 downto 0);
           AD : in STD_LOGIC_VECTOR (31 downto 0);
           Flags : in STD_LOGIC_VECTOR(3 downto 0);
           PCLoad : out STD_LOGIC;
           PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end BranchControl;

architecture Behavioral of branchcontrol is

signal Z,N,P,C,V, T: std_logic;

begin

Z <= Flags(3);        -- zero flag
N <= Flags(2);        -- negative flag
P <= not N and not Z; -- positive flag
C <= FLags(1);        -- carry flag
V <= Flags(0);        -- overflow flag

T <= 
    '1' when (PL = '1') and (BC = "0000") and (Flags = "XXXX") else -- B
    '1' when (PL = '1') and (BC = "0010") and (Flags = "1XXX") else -- BEQ
    '1' when (PL = '1') and (BC = "0011") and (Flags = "0XXX") else -- BNE
    '1' when (PL = '1') and (BC = "0100") and (Flags = "00XX") else -- BGT
    '1' when (PL = '1') and (BC = "0101") and (Flags = "11XX") else -- BGE
    '1' when (PL = '1') and (BC = "0110") and (Flags = "01XX") else -- BLT
    '1' when (PL = '1') and (BC = "0111") and (Flags = "11XX") else -- BLE
    '0';

with T select
PCValue <= PC+AD when '1',
           PC when others;
PCLoad <= T;

end Behavioral;

I am writing a simulation to test the BranchControl component, and ensure it is working as I intend. Here's my simulation:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SimulBranchControl is
end SimulBranchControl;

architecture Behavioral of SimulBranchControl is

component BranchControl is
    Port ( PL : in STD_LOGIC;
           BC : in STD_LOGIC_VECTOR( 3 downto 0);
           PC : in STD_LOGIC_VECTOR (31 downto 0);
           AD : in STD_LOGIC_VECTOR (31 downto 0);
           Flags : in STD_LOGIC_VECTOR(3 downto 0);
           PCLoad : out STD_LOGIC;
           PCValue : out STD_LOGIC_VECTOR (31 downto 0));
end component;

signal iPL : STD_LOGIC;
signal iBC : STD_LOGIC_VECTOR(3 downto 0);
signal iPC : STD_LOGIC_VECTOR(31 downto 0);
signal iAD : STD_LOGIC_VECTOR(31 downto 0);
signal iFlags : STD_LOGIC_VECTOR(3 downto 0);

signal clock : std_logic := '0';

begin

    process
    begin
        wait for 50 ns;
        clock <= not clock;
    end process;

    process
    begin
        wait until clock'event and clock='0';
        iPL<='1'; iBC<="0010"; iPC<=x"00000000"; iAD<=x"00000001"; iFlags<="0000";

    end process;

BC0: BranchControl port map(iPL=>PL, iBC=>BC, iPC=>PC, iAD=>AD, iFlags=>Flags);

end Behavioral;

For some reason, when I try and run the simulation in Vivado, I get a set of errors on the elaboration step:

INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/BranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity BranchControl
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity SimulBranchControl
ERROR: [VRFC 10-719] formal port/generic <ipl> is not declared in <branchcontrol> [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-704] formal pl has no actual or default value [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43]
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:8]
INFO: [VRFC 10-240] VHDL file /home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd ignored due to errors

Now, from what I understand this means that my entity BranchControl, and my my component of it on the Simulation have incompatible declarations, but I don't see how this is true, they seem exactly the same to me. Here's a screenshot of Vivado giving me the error.

Why is this happening? What am I doing wrong?

Answer 1

Your component mapping in the instantiation is the wrong way around; it should be:

bc0: BranchControl port map (pl => ipl, bc => ibc, pc => ipc, ad => iad, flags => iflags);