CODEWITHSUNDEEP
arraysvhdlxilinx-isedigital-logic
woo2
woo2

Reputation: 33

2-dimenstional array in expects 1 dimension

I am trying to make an array of std_logic_vectors in VHDL. The array is used in a generate statement to make a barrel shifter. Each element of the array (array, vector) should be an individually addressable bit. Here's some of my code.

Signal declarations:

type stage_t is array( 4 downto 0 ) of std_logic_vector ( 15 downto 0);
signal stages: stage_t;

In the architecture:

test_stage: for st in 0 to 4 generate
        test_bit_assign: for st_bit in 0 to 15 generate 
            test_stagemux: entity work.mux2_1 port map (
                S => amt(st),
                M0 => stages(st,st_bit), M1 =>  stages(st,st_bit+log_w),
                O => stages(st+1,st_bit)
        );
end generate;

Entity of 2:1 mux:

entity mux2_1 is
   generic ( n : INTEGER := 8);
   port (
       S : in std_logic; -- select
       M0, M1   : in std_logic;
       O        : out std_logic
    );
end mux2_1;

The error that I am getting:

Indexed name prefix type stage_t expects 1 dimensions

This happens anywhere I'm reading or writing to the stages array. How do I address bits of one of the vectors?

Upvotes: 1

Views: 1126

Answers (1)

woo2
woo2

Reputation: 33

I solved my problem by following @user1155120's second solution. stage_t is an array of vectors, and each dimension likes to be addressed on its own. stages(st) indexes the entire vector at st. stages(st)(st_bit) is the same as ( stages(st) )(st_bit).

Upvotes: 1

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