CODEWITHSUNDEEP
vhdl
y33t
y33t

Reputation: 679

VHDL st_logic_vector

signal test : std_logic_vector(135 downto 0) := x"FC255346D1B5ED025D57B49D1B44D584A1";

this signal corresponds to 'Hello World' on the console. It is not hexadecimal, obviously not binary. What is it ? I am trying to write something different.

Upvotes: 1

Views: 147

Answers (2)

neodelphi
neodelphi

Reputation: 2786

FC255346D1B5ED025D57B49D1B44D584A1 is in binary:
111111000010010101010011010001101101000110110...
111111: UART is in high level (no transmission)
      0: start bit
       00010010: This is 'H' in ASCII binary (LSB first)
               1: End of character
                010100110: This is 'e' in ASCII binary (LSB first)
etc...

Upvotes: 2

user1818839
user1818839

Reputation:

Well it begins X" ..." so it's obviously hexadecimal.

That's not the question, nor is what does it represent? which is obviously "Hello World", but how it represents it.

Figure out what's between it and the console. If just a shift register, figure out which end comes out first. write out the first 16 bits or so - or draw the waveform - remembering that a console's interface is a UART, which expects start bits, 7 or 8 bit data, possibly parity, stop bits.

Examine these to find out where Ascii "H" is buried and reverse engineer the rest of the spec from that.

Then you'll know what you have to do to substitute another message.

If you pad out the actual data with these other formatting bits in the std_logic_vector, you can replace the transmit part of a UART with a simple shift register - it's a neat hack, moving complexity out of the actual hardware and into something else - Python script or simple VHDL profram - to take a string and convert it to this format - and that's my guess what's happened here.

You might look around the rest of the project to see if you can find that python script or program...

Upvotes: 1

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