CODEWITHSUNDEEP
verilogfpgasystem-veriloghdl
surfer113
surfer113

Reputation: 55

Import data in Verilog

I would like to import data that I captured with my logic analizer using Verilog.

I dont know what would be the best way to import it to my testbench that I can test my prepared modules?

Another question is, if I should export it from logic analizer in Binary, Csv or Vdc type?

Thank you for your help!

Upvotes: 0

Views: 1886

Answers (1)

Prakash Darji
Prakash Darji

Reputation: 998

Vivado has inbuilt feature to save the ChipScope dump, in zip format.

When you manually extract that zip file, you will have the CSV file containing all signals value.

Do modify according to your usage, read it in Verilog using file management system calls!

write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]

I'm talking about that zip which is generated by this command.

  1. Generate the zip file using this command, write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]
  2. Extract that zip file and see for waveform.csv
  3. Convert it into xlsx to see and make any change if require
  4. Again convert to csv, and open in testbench using file operations.

Note : Remove signal name, and extract all vectors. assign in testbench accordingly.

Upvotes: 1

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