CODEWITHSUNDEEP
verilogsystem-verilogfixed-point
GloveTree
GloveTree

Reputation: 381

Signed Fixed Point Numbers Inequalities in Verilog

I am having problems with a verilog module in which I need to check that a fixed point number is within a set range but I am having unexpected behaviour. Here is a simplified version of what I am trying to accomplish:

reg signed [4:0] signedmaxBound =     5'sb01010; // 10
reg signed [4:0] currentValue = 5'sb00000; // 0

if (currentValue > -maxBound & currentWeight < maxBound)
    // Execute Code

I would just like to know if this code would accomplish the expected task (I have eliminated the issue to the module containing this code). I am not sure if -maxBound would perform the twos compliment operation correctly to represent the negative value.

Additionally I am unsure if the comparitor operators take sign into effect. i.e in this simplified format 10 is represented by 01010 and -15 is represented by 10000. 10 > -15 however 01010 is NOT larger than 10000.

Upvotes: 0

Views: 330

Answers (1)

dave_59
dave_59

Reputation: 42698

Your problem is you are using the bit-wise & operator instead of the logical && operator, which has higher precedence than the relational operators. So what what you are writing gets interpreted as

(currentValue > ((-maxBound) & currentWeight)) < maxBound)

This is not what you want. You want

(currentValue > -maxBound && currentWeight < maxBound)

which gets interpreted as

(currentValue > (-maxBound)) && (currentWeight < maxBound)

And the relational operators look at the signed-ness of their operands - they both need to be signed to do a signed comparison.

Upvotes: 2

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