CODEWITHSUNDEEP
vhdl
Alice1nw0
Alice1nw0

Reputation: 69

Initial value of unsigned in VHDL

I am using Altera Max plus II, writing in VHDL.

In the architecture I am given this command: 

signal count_value : unsigned (3 downto 0);

I noticed that the initial value of count_value is 0000. How can I change it?

EDIT: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all ;

entity decade_counter is
   port ( clk : in std_logic;
   q : out unsigned(3 downto 0) );
end entity decade_counter;

architecture rtl of decade_counter is
  signal count_value : unsigned(3 downto 0);
  begin
    count : process (clk) is
    begin
    if rising_edge(clk) then
      if count_value = 9 then
         count_value <= "0000";
      else
         count_value <= count_value + 1;
     end if;
   end if;
   end process count;
   q <= count_value;
end architecture rtl;

I have this code which is a BCD Counter from 1 to 9. I want to modify it so that it goes from 7 to 12. That's the reason why I want count_value to initialize at 0111.

Thanks in advance

Upvotes: 0

Views: 7764

Answers (2)

Staszek
Staszek

Reputation: 951

First - don't use std_logic_arith. It is not part of the standard, and often generates problems. Use numeric_std instead.

Second - initialization. You can do it in two ways:

  1. Init value at declaration of the signal. This is possible, but you must check if your device support it. If you want your code to be portable, use second method.

  2. Reset. Preferably synchronous, as it is usually part of the logic.

Example (haven't checked it, but should work):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;

entity decade_counter is
  port ( 
    clk : in std_logic;
    reset_n: in std_logic;
    q : out std_logic_vector(3 downto 0)
  );
end entity decade_counter;

architecture rtl of decade_counter is
  signal count_value : unsigned(3 downto 0);
  -- Possibly:
  -- signal count_value : unsigned(3 downto 0) := "0111";
begin
  count : process (clk) is
  begin
    if rising_edge(clk) then
      if resetn = '0' then
        count_value <= "0111";
      else
        if count_value >= 12 then
          count_value <= "0111";
        else
          count_value <= count_value + 1;
        end if;
      end if;
    end if;
  end process count;

  q <= std_logic_vector(count_value);

end architecture rtl;

Upvotes: 1

Dasha Sham
Dasha Sham

Reputation: 73

If it be that you want to provide some value to it at build time.I suggest you try this method

signal count_value : unsigned (3 downto 0) := "xxxx";

This "xxxx" could be any std_logic_Vector value you want

Hope it helps!

Upvotes: 0

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