Computed dependencies in make pattern rules

Question

With this simplified example Makefile

PHONY: all
all: prog_main

prog_main.c:
    echo 'int module(); int main(){return module();}' > $@

module.c:
    echo 'int module(){return 0;}' > $@

main_objects := module.o

prog_%: prog_%.o $(%_objects)
    $(CC) -o $@ $< $($*_objects)

a make will fail, because

• the syntax $(%_objects) is not supported by make and ignored,
• module.o is not a dependency of prog_main,
• make sees no need to compile module.o, and
• the link fails, because there is no module.o.

Is there a way to tell make, that each prog_% depends on prog_%.o and the targets listed int the variable %_objects?

Answer 1

You can't do what your describing as make expands % and variables at different times during processing. But you could replace the line: main_objects := module.o with prog_main: modules.o. If you did that, then module.o would appear in $^ in the prog_%: recipes. So you would have something like:

.PHONY: all
all: prog_main

prog_main.c:
    echo 'int module(); int main(){return module();}' > $@

module.c:
    echo 'int module(){return 0;}' > $@

# main_objects := module.o
prog_main: module.o


prog_%: prog_%.o
    $(CC) -o $@ $^