Warnings XST1293 and XST1896 during synthesis

Question

I am currently working on a game using VHDL as a programming language. I have been able to avoid laches from the start but on this one, I am completely lost...

I try to increment the level number when my small Mario reaches the end platform (to switch to the next level). So when he reaches this platform the signal nextLevel_i worth '1'.

I have implemented the code as follow:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use     IEEE.NUMERIC_STD.all;

entity level is
    port (
            clk_i                   : in std_Logic;
            reset_i             : in std_Logic;
            nextLevel_i         : in std_Logic;
            elem01_o                : out std_logic_vector (13 downto 0);
            elem02_o                : out std_logic_vector (13 downto 0);
            elem03_o                : out std_logic_vector (13 downto 0);
            elem04_o                : out std_logic_vector (13 downto 0);
            elem05_o                : out std_logic_vector (13 downto 0);
            elem06_o                : out std_logic_vector (13 downto 0);
            elem07_o                : out std_logic_vector (13 downto 0);
            elem08_o                : out std_logic_vector (13 downto 0);
            elem09_o                : out std_logic_vector (13 downto 0);
            elem10_o                : out std_logic_vector (13 downto 0);
            elem11_o                : out std_logic_vector (13 downto 0);
            elem12_o                : out std_logic_vector (13 downto 0);
            elem13_o                : out std_logic_vector (13 downto 0);
            elem14_o                : out std_logic_vector (13 downto 0);
            elem15_o                : out std_logic_vector (13 downto 0);
            elem16_o                : out std_logic_vector (13 downto 0);
            elem17_o                : out std_logic_vector (13 downto 0);
            elem18_o                : out std_logic_vector (13 downto 0);
            elem19_o                : out std_logic_vector (13 downto 0);
            elem20_o                : out std_logic_vector (13 downto 0)
        );
end level;

architecture Behavioral of level is
    signal currentLevel_s       : integer range 0 to 127 := 0;
begin

processLevel : process (currentLevel_s)
begin
    elem01_o <= (others => '0');
    elem02_o <= (others => '0');
    elem03_o <= (others => '0');
    elem04_o <= (others => '0');
    elem05_o <= (others => '0');
    elem06_o <= (others => '0');
    elem07_o <= (others => '0');
    elem08_o <= (others => '0');
    elem09_o <= (others => '0');
    elem10_o <= (others => '0');
    elem11_o <= (others => '0');
    elem12_o <= (others => '0');
    elem13_o <= (others => '0');
    elem14_o <= (others => '0');
    elem15_o <= (others => '0');
    elem16_o <= (others => '0');
    elem17_o <= (others => '0');
    elem18_o <= (others => '0');
    elem19_o <= (others => '0');
    elem20_o <= (others => '0');
    case currentLevel_s is
        when 1 =>
            elem01_o <= "11111001010000";
            elem02_o <= "01110000110000";
            elem03_o <= "01110001010000";
            elem04_o <= "01110001110000";
            elem05_o <= "01110010010000";
            elem06_o <= "01110010110000";
            elem07_o <= "01110011010000";
            elem08_o <= "01110011110000";
            elem09_o <= "01110100010000";
            elem10_o <= "01110100110000";
            elem11_o <= "01110101010000";
            elem12_o <= "01110101110000";
            elem13_o <= "01110110010000";
            elem14_o <= "01110110110000";
            elem15_o <= "01110111010000";
            elem16_o <= "01110111110000";
            elem17_o <= "01111000010000";
            elem18_o <= "01111000110000";
            elem19_o <= "01110011101101";
            elem20_o <= "01110100001100";
        when 2 =>
    elem01_o <= "00010000010010";
        when others =>
            elem01_o <= "00100001010000";
            elem02_o <= "11111001010000";
    end case;
end process processLevel;

----------------------
-- nextLevel Logic
----------------------
processNextLevel : process (clk_i, reset_i)
begin
    if (reset_i = '1') then 
        currentLevel_s <= 0;
    elsif rising_edge(clk_i) then
        if (nextLevel_i = '1') then
            currentLevel_s <= currentLevel_s + 1;
        end if;
    end if;
end process processNextLevel;

end Behavioral;

Note: currentLevel_s is declared as follow:

signal currentLevel_s       : integer range 0 to 127 := 0;

I have then launched the synthesis and I get the following results:

I think this result occurs because I do not affect a value to currentLevel_s (no else clause after the if (reset_i = '1') then). I simply want to keep the current value if the condition is not filled.

Any ideas how to solve these warnings ?

Answer 1

This is an easy one: You only do something when currentLevel_s is 1 ("01") or 2 ("10"). All other values don't matter. The synthesis tool optimizes away all other values.

Try adding when 127 => [something].

Or just

signal currentLevel_s : integer range 0 to 3 := 0;

    if nextLevel_i = '1' and currentLevel_s < 3 then
        currentLevel_s <= currentLevel_s + 1;
    end if;