CODEWITHSUNDEEP
c++gccassemblybinaryx86
Shuzheng
Shuzheng

Reputation: 13850

How to enforce GCC to translate volatile inline assembly statements in a linear fashion?

How to enforce GCC to translate volatile inline assembly statements in a linear fashion?

I know that making inline assembly statements both volatile and memory dependent will prevent GCC from reordering them.

However, nothing is said whether GCC will place these assembly statements linearly in the output file?

Suppose I have the following inline assembly statements (in pseudo code):

[...]
volate&mem_dependent_inline_asm_statement_1
volate&mem_dependent_inline_asm_statement_2
[...]
volate&mem_dependent_inline_asm_statement_n
[...]

Then I'm guaranteed that GCC will preserve their ordering. But how can I be certain that GCC will not output:

[...]
jmp label_1
label_2:
[...]
asm_statement_n
[...]
label_1:
asm_statement_1
asm_statement_2
[...]
jmp label_2

I know my example is kinda obscure, but my application of tamper-proofing at runtime depends on a block of inline assembly statements being translated to a corresponding block of assembly statements with ordering preserved.

In other words, I want output like this:

[...]
asm_statement_1
asm_statement_2
[...]
asm_statement_n
[...]

Any ideas?

Upvotes: 2

Views: 407

Answers (1)

Bruno Alexandre Rosa
Bruno Alexandre Rosa

Reputation: 589

Unfortunately that is not possible.

From the gcc docs:

Do not expect a sequence of asm statements to remain perfectly consecutive after compilation, even when you are using the volatile qualifier. If certain instructions need to remain consecutive in the output, put them in a single multi-instruction asm statement.

Upvotes: 3

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