CODEWITHSUNDEEP
verilog
skream117
skream117

Reputation: 11

Do not mix blocking and non-blocking assignments in the same block?

Is it true or false in Verilog? I do not understand what does it mean by mixing..Does it changes the output directly if it works?

Upvotes: 1

Views: 1978

Answers (1)

dave_59
dave_59

Reputation: 42616

The rule needs to be clarified.

Do not assign the same variable using both blocking and non-blocking assignments within the same block. The problem usually manifests itself when describing an asynchronous reset. 

always @(posedge clk or negedge rst)
  if (!reset)
    q = 0;
  else
    q < = d;

If the two events occur at the same time, but q<= d gets processed before the q=0, then there is a pending update to q after it gets set to 0, so that gets lost. There are a number of other scenarios.

Upvotes: 3

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