Reputation: 338
It is easy enough to find the answer for Windows, Linux and OSX on the web, but how about on commercial UNIX operating systems like AIX (on POWER), HP-UX (on Itanium) and Solaris (on SPARC). Experimenting with false cache line sharing code is not the answer I'm looking for.
Edit: Added the CPU architectures.
Upvotes: 0
Views: 1200
Reputation: 328
You can have a look at the hwloc library (BSD license) which gives this kind of information for different systems and architectures. You can either use the command line tool lstopo or the provided API (see documentation).
Upvotes: 0
Reputation: 30823
For Solaris (on both SPARC and x86 architectures) you can use that command:
$ prtpicl -v -c cpu | grep -i cache-line-size
:l1-dcache-line-size 0x40
:l1-icache-line-size 0x40
:l2-cache-line-size 0x40
Upvotes: 2
Reputation: 283684
If you're trying to optimize performance, then benchmarking is exactly what you should do. For an example, see ATLAS.
If you're not trying to optimize performance, why do you care about the cache line size, and do you also care about the number of lines and the associativity?
What CPU architectures do you need to support?
Upvotes: 2