CODEWITHSUNDEEP
configurationdisplaystm32f4
vionyst
vionyst

Reputation: 517

PLL of DSI-to-LVDS Bridge with a STM32F4 doesn't work

I am trying to drive a SN65DSI84 Bridge MIPI-to-LVDS with a STM32F469 microncontroller. Basically, my STM32 provides the DSI data and the SN65DSI84 converts it to the LVDS format.

The issue

Today, I manage to communicate through I2C with my SN65DSI84 to configure its registers but I don't succeed to make its PLL to lock.

Just for you to understand, the SN65DSI84 needs a clock for the LVDS output (LVDS pixel clock). This clock, as you can read it at the page 14 of the datasheet, may come from an external source or directly derived from the DSI channel. I am using the last option by setting the bit 0 of the CSR 0x0A register. The thing is that when I enable the PLL through the 0x0D register, the bit in the 0x0A register that is supposed to tell me that the PLL is indeed enabled doesn't set.

What I have done so far

Ok so in the first place my first concern is to have the PLL to lock. If I understand right the datasheet, achieving this doesn't require to configure all the registers of the bridge but only those located at the addresses 0x09, 0x0A, 0x0B and 0x0D.

In my program, I made a function that allows me to configure the registers located at the adresses 0x0A, 0x0B and 0x0D. Briefly, here is the algorithm :

  1. I disable the PLL by sending 0x00 at the address 0x0D and I wait 3ms;
  2. I send the Byte 0x01 at the address 0x0A (the clock source for the LVDS pixel clock is derived from the MIPI D-PHY Channel and the LVDS pixel clock is in the range [25 MHz ; 37.5 MHz]);
  3. I send the Byte 0x08 at the address 0x0B (divide the DSI clock by 2);
  4. I enable the PLL by sending 0x01 at the address 0x0D;
  5. I reset the bridge by sending 0x01 at the address 0x09 since, according to the description of this register (page 23) :

This bit automatically clears when set to '1' and returns zeros when read. This bit must be set after the CSR's are updated...

  1. I am waiting for the PLL to be enabled by reading and waiting the bit 7 to be set at the 0x0A address. But this bit never set.
  2. I am supposed to wait 3ms

Note : After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock.

but I never reach this point since I am in the loop at the previous point 6. And if I don't check the bit 7 at 0x0A address and bypass the point 6, it doesn't seem to work since I don't see the clock on the LVDS clock through the LVDS connector.

I checked the value of my registers (by reading them) and their value is correct.

Since it didn't seem to work and according to the description of PLL_EN register located at the address 0x0D (p. 24) :

[...]. The input clock source must be active and stable before the PLL is enable

I thought that the issue may come from the DSI side (STM32F4 side) but here is what I do before the steps explained above.

  1. I enable the DSI Host peripheral (configuration made via STM32CubeMx) ;
  2. I enable the LTDC peripheral (configuration made via STM32CubeMx) ;
  3. I start the DSI module.

I checked that no error occurred during those initializations and all seems to be ok. I can't check visually the DSI clock since I don't have physically access to the DSI clock PINs si I can't tell if the DSI clock is indeed working. But, tell me if I am wrong, to be sure that it is working properly, I checked the DSI Host PHY Control Register (DSI->PCTLR) to make sure that the CKE bit is enable (page 616 of the STM32F469 Reference Manual). And it is.

Anyway I don't really know what I can do more now. The SN65DSI84 doesn't seem to be enabled (or to lock) and I don't know why. To me the issue may come from all sides : - Wrong DSI initialization (stm32 side) ; - Wrong configuration of the bridge (sn65dsi84 side) ; - Other ?

Thanks in advance for your help !

Note : I did not provided program code yet to not make this post too confusing since there is a lot to copy. Anyway, do not hesitate to ask me some part you would like to see, I will provide it.

Upvotes: 1

Views: 1021

Answers (1)

vionyst
vionyst

Reputation: 517

After a few time (and a bit of help of Texas Instrument) I partially solved my issue. I had wrongly set the CHA_DSI_CLK_RANGE register (0x12 address). I used the "lane_byte_clock" value of the DSI Host instead of the DSI "DDR Clock" value resulting that the PLL never locked (mismatch between the DSI clock value, the LVDS pixel clock value and the DSI clock divider).

For those who are interested in this, see page 75 of the ST Application Note 4860 about the DSI Host and I recommend for those who are trying to drive this component to use the DSI Tuner tool from Texas Instrument.

Now I have the pattern picture displayed but my screen is not stable (flash, weird artifacts.... certainly because the timing parameters are not set correctly, I guess).

Thanks !

Upvotes: 1

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