How does idle(halt) state different then sleep state in Processor states?

Question

As there are 4 processor state C0-C4. but i'm not getting a difference between idle state and sleep state?

• will idle state maintain a cache coherent?
• will sleep state maintain a cache coherent?
• And what is stop-clock?

I am asking all these question related to power saving in linux kernel?

Answer 1

I'm ignorant regarding the Linux aspect of your question, the only valuable information I can add is taken directly from the ACPI 5.0 specification.

The ACPI defines n possible processor power management states: C0, C1, C2, C3, ... Cn.
They are not limited to four states but the first four (C0 - C3) define the all the possible semantics (what does it imply to enter a given Cx state) - the extended states (C4 - Cn) can have different enter/exit latencies and power savings but they must reuse one of the C0 - C3 semantics.

8.1.5 Additional Processor Power States
ACPI introduced optional processor power states beyond C3 starting in ACPI 2.0.
[...]
These additional power states are characterised by equivalent operational semantics to the C1 through C3 power states, as defined in the previous sections, but with different entry/exit latencies and power savings.

Sleeping vs Active

Each of the C0 - C3 states can either be of type Active or Sleeping.
An active type state is one such that the CPU keeps executing instructions, conversely a sleeping type state is one where instructions are not executed.

Don't confuse the word Sleeping here with the same word in Sleeping state - The first denotes the type of a CPU state, the latter denotes a Sx state (a state affecting the whole system).

The Global and System state

The CPU C0 - C3 states are only defined when in the G0/S0 state.
This means that the system as a whole must be powered up and active.
Check the ACPI specifications for a complete description of these states.

The Sx states are called the sleeping states.

C0

Type: Active
Presence: Mandatory
Software visible effects: None
Cache requirements: Preserved, Coherence
Require extra CPU hardware support: No

When in this state the CPU executes instructions.
The OSPM (OS Power Manager) can throttle the CPU by duty cycling its clock.
The IA (Intel Architecture, x86 and x86-64) have numerous throttling mechanisms including a pin called STPCLK# used to modulate the running frequency and enter a Px state (Performance state).

C1

Type: Sleeping
Presence: Mandatory
Software visible effects: None
Cache requirements: Preserved, Coherence
Require extra CPU hardware support: No

The specifications mandate that an instruction must be available to enter this state (e.g. hlt for IA) and that the latency must be negligible.

The CPU can exit this state for whatever reason but it must always exit this state upon an interrupt.

C2

Type: Sleeping
Presence: Optional
Software visible effects: None
Cache requirements: Preserved, Coherence
Require extra CPU hardware support: Chipset

This state has higher latency and power saving than C1.

The CPU can exit this state for whatever reason but it must always exit this state upon an interrupt.

C3

Type: Sleeping
Presence: Optional
Software visible effects: Yes
Cache requirements: Preserved
Require extra CPU hardware support: Chipset

This state has higher latency and power saving than C2.

The CPU can exit this state for whatever reason but it must always exit this state upon an interrupt or when another agent attempt to drive the bus to write into memory (the latter only if enabled by the OSPM).

The peculiar reasons of exit are due to the fact that cache coherence is not preserved, the OS can work around this by invalidating all the caches or waking up the CPU when a bus master is about to access the memory (thereby re-enabling cache coherence for the sleeping processor).

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Terminology

The C1 - Cn states are called idle states because they are used when the OS is idle.
C0 is the active state and under this state is possible to implement m Performance states called P0 - Pm.
These are CPU related states - idle states refer to CPU states.

The system as a whole can be in one of the sleeping state S0 - S5.
These states are grouped into Gx global states that more closely resemble the user experience.
These are system states - sleeping states refer to the system as a whole.

Stop-clock

The only thing I can think of when reading the work "stop-clock" is the STPCLK# pin, introduced with the 486DX and used to enter the C2 state or modulate the C0 state.
When asserted, with the help of the chipset, the CPU would stop most of its internal units - not all of them but more than the single use of hlt (that enters the C1 state).