CODEWITHSUNDEEP
system-verilogsystem-verilog-assertions
Adam Billal Guergachi
Adam Billal Guergachi

Reputation: 19

How to check if a signal does not change using Immediate Assertions in SystemVerilog Assertions

I'm new to SystemVerilog Assertions and I know that I can check if a signal doesn't change between clock ticks using Concurrent Assertions:

assert property (@(posedge clk) enable == 0 |=> $stable(data));

But how would I do so continuously using Immediate Assertions? This is an example that I found online but I'm not sure if it's what I need and how it works:

assign not_a = !a;
always_comb begin : b1
    a1: assert (not_a != a);
    a2: assert #0 (not_a!= a); // Should pass once values have settled
end

Upvotes: 1

Views: 4400

Answers (1)

dave_59
dave_59

Reputation: 42623

What you are asking for does not make any sense. If it a signal never can change, then it must be a constant. With the example you show, a1 might fail - there is a race condition between a and not_a. a2 is deferred assertion - it takes care of the race and will never fail. But the problem with both these assertions is that if a changes at some time, a2 never fails and you may are may not see a failure with a1

Upvotes: 1

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