CODEWITHSUNDEEP
testingverilogiverilog
NoName
NoName

Reputation: 10334

Verilog: === Operator Not Working

I have a wire:

wire module3Output;

In the end, I test the binary on the wire using:

initial
    begin
          if (module3Output === 1)
               #1 $display("PASS: module3Output=%b", module3Output);
          else
               #1 $display("FAIL: module3Output=%b", module3Output);
    end

Output:

FAIL: module3Output=1

Why is it failing when it clearly shows module3Output=1?

I can post full code if required.

Upvotes: 0

Views: 196

Answers (1)

NoName
NoName

Reputation: 10334

Found the problem after a cold beer.

The delay needs to be put before the if-statement in order to give time for the data to pass into the wire module3Output. At time unit 0, module3Output's value is 0 (by default), so the if-condition fails and the program goes into the else-condition. However, after a delay before the $display command, the data has reached module3Output and its value becomes 1, so it prints 1.

Fix'd Code:

initial
     begin
           #1 if (module3Output === 1)
                   $display("PASS: module3Output=%b", module3Output);
              else
                   $display("FAIL: module3Output=%b", module3Output);
     end

Upvotes: 1

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