CODEWITHSUNDEEP
yosys
EEliaz
EEliaz

Reputation: 359

Yosys gives syntax error on 2d interface

I get "syntax error" on 2D interface declaration in Yosys, even with the "-sv" flag.

Is there a way to make Yosys accept the next syntax?

module somename #(
     parameter WDT = 3,
     parameter CNT = 2
) (
     input [WDT-1:0] in_a [CNT-1:0],
     output [WDT-1:0] out_b [CNT-1:0]
);

Thanks!

Upvotes: 2

Views: 701

Answers (1)

CliffordVienna
CliffordVienna

Reputation: 8235

Yosys's read_verilog -sv only supports a tiny subset of SystemVerilog. Array ports are not supported.

If you have access to the Verific library then you can build Yosys with Verific support and use that to read SystemVerilog sources:

verific -sv test.sv
verific -import somename

Upvotes: 2

Related Questions