CODEWITHSUNDEEP
verilogiverilog
user2417339
user2417339

Reputation:

Test Bench not reaching last test case in verilog

I wrote the following test bench to test my Verilog code:

module HalfAdder_Test;
wire sum;
wire carry;
reg a = 0;
reg b = 0;

initial begin
    $dumpvars(0, HalfAdder_Test);

    # 10 a = 0; b = 0;
    # 30 a = 1; b = 0;
    # 50 a = 0; b = 1;
    # 70 a = 1; b = 1;

    # 90 $stop;
end

HalfAdder ha (a, b, sum, carry);

initial begin
    $monitor("a: %h, b: %h, sum: %h carry: %h", a, b, sum, carry);
end
endmodule

module FullAdder_Test;
wire sum;
wire carry;
reg a = 0;
reg b = 0;
reg c = 0;

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, FullAdder_Test);

    # 0 a=0; b=0; c=0;
    # 10 a=1; b=0; c=0;
    # 20 a=0; b=1; c=0;
    # 30 a=1; b=1; c=0;
    # 40 a=0; b=0; c=1;
    # 50 a=1; b=0; c=1;
    # 60 a=0; b=1; c=1;
    # 70 a=1; b=1; c=1;
    # 80 a=0; b=0; c=0;

    # 90 $stop;
end

FullAdder fa (a, b, c, sum, carry);

initial begin
    $monitor("a: %h, b: %h, c: %h, sum: %h carry: %h", a, b, c, sum, carry);
end
endmodule

When I run the test I never get an output for my # 70. This is surprising to me because I don't get any errors and everything seems to be running fine so I can't figure out why it wouldn't reach the last test. Here is what my output looks like: enter image description here

Also another thing to note is that I never get the output in my console for the FullAdder_Test (this line):

$monitor("a: %h, b: %h, c: %h, sum: %h carry: %h", a, b, c, sum, carry);

Upvotes: 0

Views: 301

Answers (1)

user2417339
user2417339

Reputation:

I figured it out. I had another Test file that was compiling and ending the program early. It turns out if you have one file that ends a test at a certain time (with $stop) it will end ALL tests at that time.

Upvotes: 1

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