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for-loopverilogcomparator
Ashutosh Jain
Ashutosh Jain

Reputation: 23

109 bit tree comparator with generate and for loop

I am trying to write a Verilog code for the 109-bit tree comparator, but I am still new to the generate loop.

Here is the block diagram for the 109-bit tree comparator.

I have written some code so far, but I am getting some errors. Also, I am not sure if I can use 2-d arrays for g and l signals?

parameter NUM_OF_BITS = 109;
parameter NUM_OF_LEVELS = 7;
genvar i;

for (x=0; x<NUM_OF_LEVELS; x=x+1) begin:
    generate for (i=0; i<NUM_OF_BITS/((2*x)+1); i=i+1) begin: MCs
        mag_comp2_1 mc (in0[2*i+1:2*i],in1[2*i+1:2*i],g[x][i],l[x][i]);
    end
    endgenerate
    NUM_OF_BITS = NUM_OF_BITS/2;
end

Upvotes: 1

Views: 1358

Answers (3)

Ashutosh Jain
Ashutosh Jain

Reputation: 23

parameter NUM_OF_BITS = 220;
parameter NUM_OF_LEVELS = 7;
genvar x,i;

wire [NUM_OF_LEVELS:0][NUM_OF_BITS:0] g, l;

assign g[0] = in0;
assign l[0] = in1;

generate for (x=1; x<NUM_OF_LEVELS; x=x+1) begin: Ls
    for (i=0; i<NUM_OF_BITS/(2**x); i=i+1) begin: MCs
        mag_comp2_1 mc (g[x-1][2*i+1:2*i],l[x-1][2*i+1:2*i],g[x][i],l[x][i]);
    end
end
endgenerate

assign gt = g[NUM_OF_LEVELS][0];
assign lt = l[NUM_OF_LEVELS][0];

Upvotes: 0

Alper Kucukkomurler
Alper Kucukkomurler

Reputation: 1794

Why not define the interconnections in for blocks? This way it will be more convenent for you.

An incomplete example:

parameter NUM_OF_BITS = 220;
parameter NUM_OF_LEVELS = 7;
genvar i,x;

generate for (x=1; x<NUM_OF_LEVELS; x=x+1) 
begin: Ls
    wire [NUM_OF_BITS/(2**x)-1:0] output1;
    wire [NUM_OF_BITS/(2**x)-1:0] output2;
    for (i=0; i<NUM_OF_BITS/(2**x); i=i+1) 
    begin: MCs
        if (x == 1) 
        begin
            // for the first level connect inputs to the module
            mag_comp2_1 mc (input1[2*i+1:2*i],input2[2*i+1:2*i],output1[i],output2[i]);
        end
        else 
        begin
            // for other levels connect ouputs of the previous level
            mag_comp2_1 mc (Ls[x-1].output1[2*i+1:2*i],Ls[x-1].output2]2[2*i+1:2*i],output1[i],output2[i]);
        end              
    end
end
endgenerate

Upvotes: 1

Serge
Serge

Reputation: 12364

you need something like the following. generate .. endgenerate tell the compiler to unroll all the loops and conditional statements between the keywords. So, you end up with a lot of instances of the module mag_comp2_1

parameter NUM_OF_BITS = 109;
parameter NUM_OF_LEVELS = 7;
genvar i, x;

generate
  for (x=0; x<NUM_OF_LEVELS; x=x+1) begin: externloop
    for (i=0; i<NUM_OF_BITS/((2*x)+1); i=i+1) begin: MCs
        mag_comp2_1 mc (in0[2*i+1:2*i],in1[2*i+1:2*i],g[x][i],l[x][i]);
    end
   //NUM_OF_BITS = NUM_OF_BITS/2;
  end
endgenerate

Upvotes: 0

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