CODEWITHSUNDEEP
system-verilogsystem-verilog-assertions
Emman
Emman

Reputation: 1234

Systemverilog property implication with or (||) is not working as expected?

I am trying to write sytemverilog assertions for determining clock period(140MHz) with arbitrary + or - value of 0.001ns, here in this systemverilog property used "or" operator (||) for +/- deviations/changes of time periods but outputs are not as expected, can anyone explain what is the exact cause of this?, and for any value of clk_prd the assertion gets asserted which is not as expected, also please mention what is the optimal solution for this?

code snippet below,

module clock_gen();
    timeunit 1ns;
    timeprecision 100ps;  
    bit clk;
    realtime clk_prd =1000/340.0ns; //2.9411764
    //realtime clk_prd =1000/140.0ns; //7.1428571
    property SVA_clk(real clk_prd);
      time current_time;
      (('1,current_time=$realtime) |=> 
        (clk_prd <= $realtime-(current_time - 0.001ns)) ||
        (clk_prd >= $realtime-(current_time + 0.001ns))); 
    endproperty

    assert_period:assert property (@(posedge clk)SVA_clk(clk_prd))
      $display("clk pass : %0t ",$realtime); 
    else
      $warning("clk fail : %0t",$realtime);
    initial forever #7.1428 clk=!clk; 
    initial begin 
      repeat(15) @(posedge clk); 
      $finish; 
    end
    endmodule : clock_gen

Current output:

clk pass : 213 
clk pass : 355 
clk pass : 497 
clk pass : 639 
clk pass : 781 
clk pass : 923 
clk pass : 1065 
clk pass : 1207 
clk pass : 1349 
clk pass : 1491 
clk pass : 1633 
clk pass : 1775 
clk pass : 1917

Expected output

clk fail : 213 
clk fail : 355 
clk fail : 497 
clk fail : 639 
clk fail : 781 
clk fail : 923 
clk fail : 1065 
clk fail : 1207 
clk fail : 1349 
clk fail : 1491 
clk fail : 1633 
clk fail : 1775 
clk fail : 1917

(ref from link)

Upvotes: 0

Views: 334

Answers (1)

dave_59
dave_59

Reputation: 42698

There are a multitude problems with your code

  1. The timeprecision should be in 1ps for the code as written
  2. current_time should be declared as realtime
  3. Your clock generator period is 14.2, but you should have written #(7.1428ns/2)
  4. You either have +/- reversed , or <=/>= reversed.

Upvotes: 1

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