CODEWITHSUNDEEP
system-verilog
Vinayak Bhat
Vinayak Bhat

Reputation: 33

Modeling skewed delay for combinational logic

I need help to model a block with different delays for various input-output paths?

input A;
input [3:0] B, C;
output [3:0] Y;

Y = B xor C if A = 1 else Y = 0

with A->Y delay of 10us when posedge A (rise delay) and 5us when negedge A(fall delay)

and B,C - > Y delay is 1us (applicable only if A = 1)

For my case, I might need to use procedural way and assign statements might not suit.

Upvotes: 0

Views: 507

Answers (2)

Vinayak Bhat
Vinayak Bhat

Reputation: 33

Here is something that worked best for me.

`timescale 1us/1ns

module xor_w_enabled(input A, input B, input C, output Y);
wire A_delayed;
wire B_xor_C_delayed;

assign #1 B_xor_C_delayed = B^C;
assign #(10,5) A_delayed = A;

assign Y = (A_delayed == 1) ? B_xor_C_delayed : 0;

endmodule

Please let me know if I'm missing anything.

Upvotes: 1

Serge
Serge

Reputation: 12344

For non-synthesizable models you can use #delay constructs combined with `timescale to model delays. something like the following code

`timescale 1us/1us

module delayModule(A,B,C,Y);
   input A;
   input [3:0] B, C; // this should probably be output
   output [3:0] Y;

   reg [3:0]    tmpb, tmpy;

   always @(posedge A)
       #10us tmpb <= 1;
   always @(negedge A)
       #5us tmpb <= 0;

   always @* begin
     if (A == 1)
       #1us tmpy =(B^C);
   end
   assign B = tmpb;
   assign Y = tmpy;

endmodule // delayModule

Upvotes: 0

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