CODEWITHSUNDEEP
system-verilog
Rottenengg
Rottenengg

Reputation: 115

How to implement Summation equation in SystemVerilog constraints?

c=∑(a[i]*b[i]) Consider Two arrays a and b. The result,c of MAC operation of the two arrays a and b should be less than 1024. Use SystemVerilog constraints to implement above condition. Size of the two arrays can go from 1 to n and each array element stores 1 byte. We have to randomize both arrays.

Upvotes: 0

Views: 2719

Answers (1)

dave_59
dave_59

Reputation: 42698

Now that I've seen your solution in chat, I'll give you what I was thinking

constraint c_sum { c == a.sum() with (a[item.index] * b[item.index]); c < 1024;}

Upvotes: 3

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