CODEWITHSUNDEEP
questasim
Tsr
Tsr

Reputation: 11

verification using Questasim

I am trying to verify my design in Questasim and the design is in VHDL. I am using Makefile. The command is 

vcom -93 -work $(work) $(RTL) $(SVTB1) $(SVTB)

It is invoking VHDL compiler, but it is not displaying the master_driver signals.
Can anybody tell the solution?

Upvotes: 0

Views: 418

Answers (1)

Tsr
Tsr

Reputation: 11

I got one solution but I don't know whether it's a perfect one. The solution to my question is that divide SV and VHDL codes in two different folders and compile them separately. But the work folder should be same.

Upvotes: 0

Related Questions