Do data-processing instructions have latency? - Interpreting ARM Cortex A9 Timing Manual

Question

I need help with interpreting the ARM Cortex A9 Manual, regarding timing.

ARM A9 Cycle timings

Under the point "Data-processing instructions cycle timings" unit cycle times are given - when I look up the Multiplication instructions, cycles AND latency is given - does this impose that e.g. an ADD instruction does not have extra latency?

Answer 1

This is related to the pipeline depth of each execution unit. The image shows a pipeline for an out of order processor (Cortex A-15, the Cortex A9 is also an out of order processor but with a shorter pipeline). The Integer execution unit is just one cycle, so they do not have extra latency in their execution. However the Multiply execution unit has 4 cycles. This does not means that always is going to take 4 cycles, but depending on the values and number of registers used it may take 4, fewer or more cycles.

Here in the table you can see more detail in the Latency and also the throughput, for example SDIV 1 every 20 to 1 every 4 cycles

The table was taken from Cortex-A57 Software Optimization Guide The pipeline image was taken from here: Berkeley Design Technology, Inc