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Drejc
Drejc

Reputation: 531

VHDL 3-bit sequence counter with T-Flip Flops

I am new to VHDL and I can't see a solution to my problem. I want to find a VHDL code for my 3-bit sequence counter with T Flip Flop's which goes: ..,0,4,5,7,6,2,3,1,0,... I made a truth table and minimized equations for T_FF like so:

enter image description here

T0=Q2 xor Q1 xor Q0;

T1=(Q2 xor Q1) and Q0;

T2= not(Q2 xor Q1) and Q0;

Then I draw the circuit:

enter image description here

Last VHDL:

T-FLIP FLOP

library ieee;
use ieee.std_logic_1164.all;
entity tff is
  port(
        clk: in std_logic;
        reset: in std_logic;
        t: in std_logic;
        q: out std_logic
      );
end tff;

architecture behave of tff is
 -- signal q_reg: std_logic; --v registru
--  signal q_next: std_logic; --naslednje stanje
begin
 process
variable x: std_logic:='0';
 begin
wait on clk;
       if (clk' event and clk = '1') then
    if reset='1' then
    x:='0';
    else x:=t;
end if;
end if;
if (t = '1') then
q<=not x;
else 
q<=x;
end if;
end process;

end behave;
 -----------------------------------------------------------

Gray counter

library ieee;
use ieee.std_logic_1164.all;
entity tff_gray is
  port(
        clk: in std_logic;
        reset: in std_logic;
        q: inout std_logic_vector (2 downto 0)
        --q: out std_logic
      );
end tff_gray;

architecture behave of tff_gray is
component tff is
  port(
        clk: in std_logic;
        reset: in std_logic;
        t: in std_logic;
        q: out std_logic
      );
end component;

  signal i0,i1,i2: std_logic; --v registru
  --signal q_next: std_logic; --naslednje stanje
begin
i0<=q(0) xor q(1) xor q(2);
i1<=q(0) and (q(1) xor q(2));
i2<=q(0) and not(q(1) xor q(2));
    Tff0: tff port map(clk, reset, i0, Q(0));
    Tff1: tff port map(clk, reset, i1, Q(1));
    Tff2: tff port map(clk, reset, i2, Q(2));
end behave;

I wrote this bunch of code of what I found over the internet. When I compiled my code it all went through without a problem but the simulation is wrong. I went through this code a lot of times and I don't know what is wrong. If anyone has any idea please share. I have mostly watched this altera site and LBEbooks on YouTube.

Upvotes: 1

Views: 6908

Answers (1)

JHBonarius
JHBonarius

Reputation: 11261

A number of things. Firstly:

T-FF aka toggle flip flop

You've got your toggle flip-flop description incorrect. A toggle flip flop flips the output if T='1'. so:

    signal q_int : std_logic := '0';
begin
    tff_proc: process(clk) begin
        if rising_edge(clk) then
            if t='1' then
                q_int <= not q_int;
            end if;
            -- reset statement
            if reset='1' then
                q_int <= '0';
            end if;
        end if;
    end process;

    q <= q_int;

redundant code

Don't combine wait on clk and if (clk'event and clk='1') as they do the same thing. Combining will cause issues. Refer to my example above for correct instantiations.

component instantiation

You don't need to include the component tff code in your tff_gray entity. Just simply instantiate the entity directly from the library. e.g.

Tff0: entity work.tff port map(clk, reset, i0, q(0));

bidirectional ports (inout type)

Using the inout type, which you use for the q of tff_gray can give problems in simulation and implementation. It should be out.

However, you must have encountered the cannot read outputs error. This is no longer an issue in VHDL-2008, so you should compile using VHDL-2008 mode.

Alternatively, you need to use intermediate signals, like I did in the example above. E.g.

signal q_int : std_logic_vector(2 downto 0) := (others => '0');
[...]
q <= q_int;

Upvotes: 1

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