CODEWITHSUNDEEP
system-verilogmodelsim
jeremiah
jeremiah

Reputation: 117

Passing a struct as a parameter in System Verilog

The following code works fine under Modelsim when the unused localparam is removed. It produces the error below if it is left in. If it is possible to use a struct to pass parameters to a module, what am I doing wrong? Many thanks.

typedef bit [7:0] myarr[2];
typedef struct { int a; myarr bytes; } mystruct;

module printer #(mystruct ms)();

  // works fine if this is removed
  localparam myarr extracted = ms.bytes;

  initial
    $display("Got %d and %p", ms.a, ms.bytes);

endmodule 

parameter mystruct ms = '{ a:123, bytes:'{5, 6}};   

module top;
  printer #(.ms(ms)) DUT ();
endmodule

Here is the error. Compilation using vlog -sv -sv12compat produces no errors or warnings.

 $ vsim -c -do "run -all; quit" top
 Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017
 (.......)
 # ** Error: (vsim-8348) An override for an untyped parameter ('#dummyparam#0') must be integral or real.

Upvotes: 2

Views: 3308

Answers (2)

Scott Nelson
Scott Nelson

Reputation: 26

I think the problem here is that you are assigning a whole unpacked array in one statement, which is not allowed. Try changing the myarr typedef to a packed array instead.

Upvotes: 1

jeremiah
jeremiah

Reputation: 117

My workaround was to use a packed array. I didn't need to pack the whole struct.

I would happily upvote/accept someone else's answer if one appears. In particular, it would be helpful to confirm whether this is really a bug in Modelsim, or just an instance of a correct compilation error that could be made more helpful by including the location and parameter name.

Upvotes: 0

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