CODEWITHSUNDEEP
vhdl
user169808
user169808

Reputation: 513

VHDL package and std_logic_vector

I'm trying do declare a type to use in the port but i'm with a problem if I do the following I get an error that STD_LOGIC_VECTOR isn't declared 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Custom types --
package Common  is
    type Mem_in is array (2**6 to 0) of STD_LOGIC_VECTOR (11 downto 0); 
    type DinDout is range 11 downto 0;
end package Common ;
-- Use Custom Type
use work.Common.all;

entity MUX is

    Port (
        D       :   in Mem_in;
        Q       :   out DinDout;
        SEL     :   in  STD_LOGIC_VECTOR (11 downto 0)
        );
end MUX;

Why can't I use STD_LOGIC_VECTOR? If I change it to DinDout I get another problem down the line in the architecture: to_integer is not declared; indexed name is not a dindout.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Custom types --
package Common  is
    type Mem_in is array (2**6 to 0) of STD_LOGIC_VECTOR (11 downto 0); 
    type DinDout is range 11 downto 0;
end package Common ;

And the entity using package Common:

-- Use Custom Type
use work.Common.all;

entity MUX is

    Port (
        D       :   in Mem_in;
        Q       :   out DinDout;
        SEL     :   in  DinDout
        );
end MUX;

architecture Arc of MUX is
begin
    Q <= D(to_integer(unsigned(SEL)));
end Arc;

how can I add STD_logic_vector to my package OR solve these two errors: to_integer is not declared; indexed name is not a dindout?

thanks

Upvotes: 0

Views: 1105

Answers (1)

Andreas Bombe
Andreas Bombe

Reputation: 2470

You have two library units in one file (if it is a single file you have quoted). While I am not sure what happens, I guess it restarts the context with every unit.

That would mean you have to repeat library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; before use work.Common.all;.

Also 2**6 to 0 is a null range, that should be 0 to 2**6 or 2**6 downto 0.

Upvotes: 3

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