CODEWITHSUNDEEP
functionsyntaxverilog
Lerbi
Lerbi

Reputation: 225

How are functions used in Verilog?

In my FPGA/Verilog course, my professor just went over functions.

He was saying that within functions, you write the code procedurally. Then, when you want to call the function, you can either call it within an always block (ie, procedurally), or you can call it with an assign statement.

It doesn't make sense to me how a function can be written with procedural code, but then be called continuously.

If anyone has any insight to this (probably) basic question, it is much appreciated.

Upvotes: 2

Views: 9242

Answers (3)

Charles Clayton
Charles Clayton

Reputation: 17946

It's pretty much exactly the same as combinational logic blocks. You write it that way, but it's synthesized into something completely different. Consider the following:

always @* begin
    a = b + c;
    d = b + a;
end

always @(posedge clk) begin
    out <= d + in; 
end

This is exactly the same thing as:

function integer calc_d(integer b, integer c) begin
    integer a;
    integer d;
    a = b + c;
    d = b + a;
    calc_d = d; 
end
endfunction

always @(posedge clk) begin
    out <= calc_d(b, c) + in;
end

Upvotes: 4

Serge
Serge

Reputation: 12344

A function which returns a value (non-void function) is used in verilog as an operand of an expression. It encapsulates a verilog expression, which can consist of multiple statements in the function. As such it could be use in any place where expression could be used. Procedural blocks and continuous assign statements are such places.

Continuous assignment term is a historical one and its purpose is to drive values into nets (continuously change the value of the net if the input expression value changes). So, if a function is used in rhs, it just provides the value calculation based on its inputs.

so, here is an example:

function automatic reg[3:0] sum (reg[3:0] a, reg[3:0] b);
   sum =  a + b;
endfunction // b

reg [3:0] r;
wire [3:0] w;

// use function in the procedural block
always @* 
  r = sum(a, b);

// use function in the continuous assignment
assign w = sum(a,b);

Upvotes: 1

dave_59
dave_59

Reputation: 42616

There is no such thing as continuous in Verilog, or any other event driven simulation. All behavior is driven by discrete events, meaning a signal changing its value, or a waiting for a discrete amount of time to pass.

A continuous assignment in Verilog is just a way of defining an expression so that when any operand of the RHS expression changes, the expression gets evaluated and its result gets propagated to the LHS target. Any logical or arithmetic expression can include function calls.

Upvotes: 1

Related Questions