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clinuxgccmakefile
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Reputation: 19333

Compile object files in local temporary directories

I have a GNU Makefile project that has source files scattered throughout multiple directories, i.e.:

Project/common/base.c
Project/common/test.c
Project/delta/delta.c
Project/delta/bravo/alt.c

I would like to try two separate ways of generating the object files, and then linking them:

Type 1:

ARCH=arm64
Project/common/base.c       ==>     Project/common/.tmp/${ARCH}/base.o
Project/common/test.c       ==>     Project/common/.tmp/${ARCH}/test.o
Project/delta/delta.c       ==>     Project/delta/.tmp/${ARCH}/delta.o
Project/delta/bravo/alt.c   ==>     Project/delta/bravo/.tmp/${ARCH}/alt.o

Type 2:

ARCH=arm64
Project/common/base.c       ==>     .tmp/${ARCH}/Project/common/base.o
Project/common/test.c       ==>     .tmp/${ARCH}/Project/common/test.o
Project/delta/delta.c       ==>     .tmp/${ARCH}/Project/delta/delta.o
Project/delta/bravo/alt.c   ==>     .tmp/${ARCH}/Project/delta/bravo/alt.o

How can I generate a build rule like this so that I can just add more source files to a list, and have the build iterate through them, creating output/object files with the file name patterns shown above, and then linking a final binary/app with the resulting object files? I've tried a similar such approach as described in another question, but that one assumes all the source files are in the same directory.

Upvotes: 0

Views: 53

Answers (1)

roelofs
roelofs

Reputation: 2170

Based on this question, you could try the approach in the accepted answer for your second approach:

$(OBJDIR)/%.o: %.c
    $(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $<

and define $(OBJDIR) as .tmp/${ARCH}.

Upvotes: 1

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