CODEWITHSUNDEEP
caseconditional-statementsverilogcase-statement
gdagis
gdagis

Reputation: 113

Updating multiple variables in case statement

I've been looking around for a while so forgive me if maybe I'm using improper terminology...

The goal of the code is to update Aout1 and Aout0 if the input is 0, with the output corresponding to a 7-segment display, but I'm getting the following error:

"Error (10170): Verilog HDL syntax error at FourBitAdder.v(55) near text: ","; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword."

Below is a snippet of the code giving me issues...

always @*
case (A)
4'b0000 : Aout1 = 7'b1000000, Aout0 = 7'b1000000; //00

I tried changing the code to the following and while I didn't get any errors on my software, my hardware (7-segment display) isn't working like it was when I was trying to just change one variable per case.

always @*
case (A)
4'b0000 : Aout1 = 7'b1000000; 4'b0000 : Aout0 = 7'b1000000; //00

Thank you in advance :)

Upvotes: 3

Views: 7570

Answers (1)

Charles Clayton
Charles Clayton

Reputation: 17986

Use a begin and end statement after the colon.

always @* begin
    case(A)
        4'b0000: begin
            Aout1 = 7'b1000000;
            Aout0 = 7'b1000000;
        end
        4'b0001: begin
            Aout1 = 7'b0000011;
            Aout0 = 7'b0000011;
        end

    endcase
end

Upvotes: 5

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